(1) Field of the Invention
The invention relates to the formation of bipolar junction transistors and more particularly to deep sub-micron in BiCMOS integrated circuits.
(2) Description of prior art
Recent trends in integrated circuit design have seen the re-emergence of the bipolar junction transistor(BJT) as a useful companion to the metal oxide silicon field effect transistor(MOSFET) which has dominated the technology for more than a decade. The BJT, although superior in speed and current driving capability to the MOSFET, was by-passed because of its somewhat greater cost and difficulty of manufacture, and its current and space requirements, by the MOSFET. However, in recent years, the processing advancements developed for use by complementary MOSFET (CMOS) technology, have provided a favorable environment for the incorporation of the BJTs into CMOS integrated circuits. CMOS technology makes combined use of n-channel MOSFETS (NMOS devices) and p-channel MOSFETs (PMOS devices).
The obvious utilization of BJTs is for input/output(I/O) functions while relegating the logic functions to the CMOS devices. More recently, however, bipolar devices are finding their way into the logic functions themselves in the form of BICMOS logic gates, interface drivers, and even into SRAMs(static-random-access-memories). FIG. 1, taken from Wolf, S.,"Silicon Processing for the VLSI Era", Vol.2, Lattice Press, Sunset Beach, Calif., (1995), p586, illustrates the reduction in access time of SRAMs offered by bipolar and BiCMOS technology.
The great strides made in recent years towards sub-micron definition of device components, along with the advancement of polysilicon technology have removed many of the competitive obstacles of the BJT. The technology which is now emerging from CMOS is a BiCMOS technology and involves the integration of BJTs into the CMOS environment.
Newer processing techniques developed for CMOS technology have made some of the critical features of the thin film bipolar transistor easier to control, in particular the base width and the emitter area. p- and n-wells, developed for CMOS technology, have been used to provide buried collectors for BJTs within the framework of CMOS technology without the need for epitaxial layers. Examples of BiCMOS structures formed in may be found in Wolf, S.,"Silicon Processing for the VLSI Era", Vol.2, Lattice Press, Sunset Beach, Calif., (1995), p531ff. Although such bipolar structures are easily assimilated into the CMOS process, they suffers from a high collector resistance(R.sub.c) as well as high collector-base and emitter-base capacitances which compromise device performance.
Generally, high performance bipolar transistors require collectors with significantly higher doping levels than can be provided by conventional, ion implanted n- and p-wells. Unfortunately the use of a heavier implant to provide the highly doped buried collector also causes a significant increase in implant damage in the region above the collector wherein the emitter and the intrinsic base regions are subsequently formed. Damage in these regions results in serious device degradation in the form of intolerable current leakage and shorts between these elements and the collector. This shortcoming of conventional ion implantation has forced many practitioners to resort to earlier and more established methods for forming high performance BJTs--that of incorporating the buried collector by the use of an epitaxial layer.
These traditional methods involve local implantation of dopant into the region of the wafer where the collector is to be formed. An epitaxial layer is then grown over the wafer. During the epitaxial growth, the implanted material diffuses into the epitaxial layer and further into the substrate silicon. When arsenic is used as the collector dopant for an npn BJT, lateral auto-doping takes place during the epitaxial growth, requiring the use of p+ junction isolation. Although antimony is less prone to lateral auto-doping, it's solid solubility in silicon is only about one-tenth that of arsenic, making it unsuitable for high dopant concentrations. The impact of problems resulting from auto-doping become more severe as device geometries become smaller. These shortcomings in addition to the increased cost of epitaxial growth itself, are major disadvantages of the use of epitaxy to form high performance sub-micron BJTs,
Ford, U.S. Pat. No. 4,902,639 forms an npn BJT with a buried collector by first forming the heavily doped regions in the substrate and then growing an epitaxial layer. n- and p- wells are then formed for the CMOS devices and over the buried collector region. a heavily doped reach-through provides a low resistance contact to the buried collector element. The base and emitter regions are then formed along side the collector reach-through. Fabricius, et.al. U.S. Pat. No. 4,508,757 describes a method for reducing birds beak during the formation of isolation for a BJT having a collector buried in an epitaxial layer.
Joyce, U.S. Pat. No. 5,326,710 forms a lateral pnp BJT for a BiCMOS integrated circuit, using an epitaxial BiCMOS process which includes conventional npn BJTs wherein the heavily doped buried layer is used to provide retrograde dopant profiles for the lateral pnp BJT.
Grubisich, U.S. Pat. No. 5,580,798 uses two epitaxial layers to fabricate a BJT with a guard ring. The second epitaxial layer is used to develop the heavily doped buried collector.
The current invention takes advantage of the present day trend which reduces lateral device geometries to sub-micron levels, by performing a heavy ion implant of the collector dopant in a perimeter region of the active area of the BJT. Thus the emitter and base regions do not suffer damage from the implantation process. Subsequent lateral diffusion of the dopant during field oxide growth, forms the buried collector below the active area. Because of the small lateral geometries, complete filling of the active area is possible.